Indenting VHDL as other programming languages

Question

When I write VHDL Vim uses a mix of tabs and spaces which aim to align columns beneath the last parenthesis. For example, Vim will produce something like

Inst_IMem: IMem PORT MAP(
                            CLK => clk,
                            ADDR => foo,
                            DATA => bar
                        );

instead of

Inst_IMem: IMem PORT MAP(
    CLK => clk,
    ADDR => foo,
    DATA => bar
);

How can I make Vim indent VHDL as it would indent programming languages such as C and Java? I.e. a new indentation level (either a tab or say four spaces) for every new nesting level.

Answer 1

This seems to be fairly simple, you only need to use:

:let g:vhdl_indent_genportmap = 0

And you're done :-)

I found this in /usr/share/vim/vim74/indent/vhdl.vim:

" option to disable alignment of generic/port mappings
if !exists("g:vhdl_indent_genportmap")
  let g:vhdl_indent_genportmap = 1
endif

Which is used further below:

if g:vhdl_indent_genportmap
  return ind2 + stridx(prevs_noi, '(') + &sw
else
  return ind2 + &sw
endif

So if it's off (0), it will only indent a single shiftwidth, if it's on (1), it uses the location of the ( on the previous line + `shiftwidth.

This (and some other things) are also documented in :help ft-vhdl-indent; I found this page by typing :help vhdl (a number of filetypes have their own help pages).