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I'm finding some strange behaviour on indentation in VHDL, and have added a minimum example. It is very strange, as everything else seems to work perfectly with VHDL.

Does anybody know how to fix this?

The first example is of course how it should look:

comp1 : Comp
port map(a => a, b=> b);

comp2 : Comp
port map(a => a, b => b);

but after gg=G, turns into:

comp1 : Comp
port map(a => a, b=> b);

         comp2 : Comp
         port map(a => a, b => b);

Any inputs would be greatly appreciated.

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    Welcome to Vi and Vim! You can always try hacking on the indent script for your filetype, though be wary of diving into a deep rabbit hole :)
    – D. Ben Knoble
    Dec 18 '20 at 22:10
1

I don't really know much about VHDL... But looking at the VHDL indent script ($VIMRUNTIME/indent/vhdl.vim) I can see that it recognizes port map, but it seems it's only prepared to recognize the parens ( and ) in separate lines.

If you do wrap the lines, you'll see that Vim will indent it properly:

comp1 : Comp
port map(
            a => a,
            b => b
        );

comp2 : Comp
port map(
            a => a,
            b => b
        );

There's an option to control whether to align generic/port mappings, but that mostly affects the body of the map(...) statement (whether the a => a, b => b and ); will be indented.)

You can change the behavior by setting the following variable in your vimrc:

let g:vhdl_indent_genportmap = 0

If you'd like to follow up on having the whole expression in the same line (the ) closing the expression), you might want to consider contacting the maintainer of the indentation script, thought it doesn't look like that script has been touched in a few years... You might also consider filing an issue on Vim's GitHub, or posting on the vim-dev mailing list.

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